HDMP-3268 Datasheet, PDF (13/18 Pages) Agilent(Hewlett-Packard) – 3.2 Gbit/sec 68x68 Crosspoint Switch

Table 11. HDMP-3268 Pin Definitions
Name
DIN[0:67]
Type
HS_IN
Signal
High Speed Data Channel Inputs. Data channel inputs accepting 3.2 Gbit/sec data for
rerouting to high speed outputs DOUT[0:67]+ and DOUT[0:67]-. Routing is controlled by the
Address Registers.
DOUT[0:67] HS_OUT High Speed Data Outputs. High-speed data channel outputs. Routing is controlled by the
Address Registers.
CNTL
CTL_IN
Control Input. Determines whether DATA[6:0] inputs are interpreted as addresses or control
(input equalization and power off) settings. When CNTL is low the DATA[6:0] inputs are
interpreted as addresses. When CNTL is high the DATA[6:0] inputs are interpreted as input
equalization, amplitude, and power off settings.
DATA[6:0]
CTL_I/O Data Inputs and Outputs. Address, input equalization, output amplitude and power off
settings. Interpretation is determined by the state of the CNTL input. The direction of the data
(input or output) is determined by the RW pin. DATA [6] is MSB.
CH[6:0]
CTL_IN Channel Select. Selects one of the 68 control or address registers from which data is to be
written or read. CH [6] is MSB.
CS
CTL_IN Chip Select. When CS is low the crosspoint switch chip is selected and the RW and
DATA pins are enabled. This pin can be used to allow multiple crosspoint switches to operate
on a shared bus.
RW
CTL_IN Read Write. This input is used to control whether address or program data is being written
or read from the internal address and control registers. RW is 1 for Read mode and 0 for
Write mode.
WSTB
CTL_IN Write Strobe. Input write strobe for writing DATA inputs to the internal address and control
register. Data is latched into the internal registers on the rising edge of WSTB.
GND
S
Ground. Normally 0 volts.
VDD
S
Logic Supply Voltage. Normally 2.5 volts.
VCC
S
Switch Array Power Supply. Normally 2.5 volts. Used for internal PECL logic. It should be
isolated from CMOS supply.
VCC_DOUT S
High Speed Output Supply. Normally 2.5 volts. Used only for the last stage of the high-speed
transmitter output cell. VCC_DOUT should be well bypassed to a ground plane.
TERM
CTL_IN Termination. Set to high to terminate SSTL_2 I/O lines.
USE
CTL_IN Use. Selects address register bank to use to configure the switch.
SET
CTL_IN Set. Determines which address register is accessed by the CTL_I/O interface.
VREF14
REFO
LVTTL Voltage Reference Output. Nominally 1.4 V. Sets input threshold when logic inputs are
connected to LVTTL signals
VREFI
REFI Voltage Reference Input. Used with I-SSTL_2 inputs to the HDMP-3268.
VREFO
REFO Voltage Reference Output. Used with O-SSTL_2 outputs from the HDMP-3268.
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