HDMP-1032 Datasheet, PDF (3/32 Pages) Agilent(Hewlett-Packard) – 1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate

TXCLK
Tx
Rx
A) 16 BIT SIMPLEX TRANSMISSION
RXCLK0/1
REFCLK
TXCLK
Tx
Rx
RXCLK0/1
REFCLK
Rx
RXCLK0/1
REFCLK
Rx
RXCLK0/1
REFCLK
B) 16 BIT BROADCAST TRANSMISSION
MUX
Tx
TXCLK
Rx
RXCLK0/1
DEMUX
REFCLK
C) 32 BIT SIMPLEX TRANSMISSION
Tx
TXCLK
Rx
RXCLK0/1
REFCLK
Tx
TXCLK
Rx
RXCLK0/1
REFCLK
D) 32 BIT SIMPLEX TRANSMISSION
TXCLK
RXCLK0/1
REFCLK
Tx
Rx
RXCLK0/1
REFCLK
Rx
Tx
TXCLK
E) 16 BIT DUPLEX TRANSMISSION
Figure 1. Various configurations using the HDMP-1032/1034.
3
Typical Applications
The HDMP-1032/1034 chipset
was designed for ease of use
and flexibility. The customer can
tailor the use of this product
through the configuration of the
link based on specific system re-
quirements and application needs.
Typical applications range from
backplane serialization and bus
extension to cellular base stations.
All modes are built up from the
basic simplex transmission mode
as shown in Figure 1a.
For digital video transmission,
simplex links are common. The
HDMP-1032/1034 chipset can
transmit 16 bits of parallel data
in standard or broadcast simplex
mode (Figures 1a, 1b).
If the bus is 32 bits wide, the
HDMP-1032/1034 chipset is ca-
pable of sending this data word as
two separate word segments with
the use of an external mux and
demux as shown in Figure 1c. In
this mode, the transmitter and
receiver use the FLAG bit to indi-
cate the first or second word
segment. The HDMP-1032/1034
chipset may also be configured
in full duplex to achieve a 32 bit
wide bus extension. In addition,
32 bit wide data can be transmit-
ted over two parallel serial lines
as shown in Figure 1d.
Low latency bus extension of
a 16 bit wide data bus may be
achieved using the full duplex
configuration (Figure 1e). In this
mode, link startup is achieved
by exchange of control words.