HDMP-1032 Datasheet, PDF (16/32 Pages) Agilent(Hewlett-Packard) – 1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate

HDMP-1032 (Tx) Pin Definition
User Mode Options
Name
Pin
Type
TXFLGENB 10
I-TTL
ESMPXENB 11
I-TTL
TXDATA
5
I-TTL
TXCNTL
4
I-TTL
High-Speed Serial/Parallel I/O
HSOUT+
20
HS_OUT
HSOUT-
19
TX[0]
TX[1]
TX[2]
TX[3]
TX[4]
TX[5]
TX[6]
TX[7]
TX[8]
TX[9]
TX[10]
TX[11]
TX[12]
TX[13]
TX[14]
TX[15]
46
I-TTL
47
50
51
52
53
54
55
58
59
60
61
62
63
2
3
TXFLAG
6
I-TTL
Signal
Flag Bit Mode Select: When this input is high, the TXFLAG bit
input is sent as an extra 17th data bit during data word transfers.
As an example, the flag bit can be used as an even or odd word
indicator for 32 bit transmission. The RXFLGENB input on the Rx
chip must be set to the same value as the TXFLGENB pin.
Enhanced Simplex Mode Enable: Enables scrambling of the Flag
Bit encoding. The ESMPXENB pin on the Rx chip must be set to
the same value. This mode should be enabled unless compatibility
with previous versions of G-Link (i.e. HDMP-1024/1014) is desired
desired which don’t have this feature.
Transmit Data Word: This input tells the chip that the user has
valid data to be transmitted. When this pin is asserted and
TXCNTL is low, bits TX[0-15] and optionally TXFLAG are encoded
and sent as a data word.
Transmit Control Word: This input tells the Tx chip that the user
is requesting a control word to be transmitted. When this pin is
asserted, bits TX[0-13] are sent as a control word. If TXCNTL and
TXDATA are asserted simultaneously, TXCNTL takes precedence.
Idle words are transmitted if both TXDATA and TXCNTL are low.
Serial Data Output: These pins form a buffer line logic driver,
which is a 50 Ω terminated PECL compatible output.
Word Inputs: When sending data words, TX[0-15] are serialized.
When sending control words, TX[0-13] are serialized.
Flag Bit: When TXFLGENB is active, this input is sent as an extra
data bit in addition to the 16 data word bits. When TXFLGENB is
not asserted, this input is ignored and an alternating internal flag
bit is transmitted to allow the Rx chip to perform error detection
during data word transfers. The Flag Bit is not sent when a control
word is transmitted.
16