HDMP-1032 Datasheet, PDF (26/32 Pages) Agilent(Hewlett-Packard) – 1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate

Integrator Capacitor and Supply
Bypassing/Grounding
Figure 12 shows the PLL inte-
grator capacitors, power supply
capacitors and required ground-
ing for the Tx and Rx chips.
a result, all of the separate power
supplies (V_CC, V_CC_TTL, and
V_CC_HS) can be connected onto
this plane. The bypassing of V_CC
to ground should be done with a
0.1 µF capacitor (C1).
Integrator Capacitor
An integrator capacitor (C2) is
required by both the Tx and Rx
for them to function properly.
This cap is used by the PLL for
frequency and phase lock, and di-
rectly sets the stability and lockup
times. A 0.1 µF capacitor is recom-
mended for each DIV1/0 setting.
Supply Bypassing/Grounding
The HDMP-1032/34 chipset has
been tested to work well with a
single power plane, assuming that
it is a fairly clean power plane. As
TTL and HighSpeed
I/O I-TTL and O-TTL
These I/O pins are TTL compatible.
A simplified schematic diagram of
the I/O cells is shown in Figure 13.
High-Speed Interface: HS_IN and
HS_OUT
The simplified schematic diagrams
of HS_IN and HS_OUT are shown
in Figure 14. The HS_IN input cell
is implemented with internal 50Ω
resistors between the differential
input lines HSIN± to GND_HS.
The HSIN± inputs have internal
bias provided and the signals are
AC coupled in with 0.1µF capaci-
tors. It is recommended that
differential signals be applied
across the HSIN± inputs (Figure
15a), although a single-ended
connection is acceptable. In this
case, the unused input must be
terminated with 50Ω AC coupled
to ground.
The HS_OUT output cell is
designed to deliver PECL swings
directly into 50Ω. The output
impedance is matched to 50Ω and
has a VSWR of less than 2:1 to
above 2 GHz. This output is
ideal for driving the HS_IN input
through a 50Ω cable and a
0.1 µF coupling capacitor. The
HS_OUT driver can also be
V_CC_A2
C1
C1
C1
C1
C1
C1
C1
HDMP-1032
C1
Tx
C1
C1
C2
C1
C1
C1
C1
V_CC_A1
C1 = BYPASS CAPACITOR
C2 = PLL INTEGRATOR CAPACITOR
0.1 µF
0.1 µF
NOTE: V_CC_A PINS SUPPLY VOLTAGE SHOULD
COME FROM A LOW NOISE SOURCE.
Figure 12. HDMP-1032 (Tx) and HDMP-1034 (Rx) Power Supply Pins.
26
HDMP-1034
Rx
C1
C2
C1
C1
V_CC_A