HDMP-1032 Datasheet, PDF (17/32 Pages) Agilent(Hewlett-Packard) – 1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate

HDMP-1032 (Tx) Pin Definition (continued)
PLL/Clock Generator
Name
Pin
Type Signal
TXCAP0
32
C
Loop Filter Capacitor: A 0.1 µF min. loop filter capacitor, C2, must
TXCAP1
33
be connected across TXCAP0 and TXCAP1 for all combinations of
TXDIV1/TXDIV0. See Figure 12.
TXCLK
37
I-TTL Transmit Word Clock Input: When TCLKENB is low, this word rate
clock input is phase locked and multiplied to generate the high-
speed serial clock. When TCLKENB is high, the PLL is bypassed
and TXCLK becomes the serial clock.
TXDIV0
TXDIV1
26
I-TTL VCO Divider Select: These pins program the VCO divider chain to
27
operate at full, half or quarter speed. See Typical Operating Rates
table and Figure 2.
LOCKED
12
O-TTL Locked to TXCLK: This pin goes high when the transmit PLL
achieves frequency lock to the TXCLK signal.
Power Supply/Ground
V_CC
13
S
Logic Power Supply: Normally 3.3 volts. This power supply is
24
used for the internal transmitter logic.
36
49
64
V_CC_TTL
8
S
TTL Power Supply: Normally 3.3 volts. Used for all TTL transmitter
41
input and output buffer cells.
V_CC_HS
17
S
Serial Output Power Supply: Normally 3.3 volts. Used for Serial
Output pins.
V_CC_A1
V_CC_A2
GND
31
S
Analog Power Supply: Normally 3.3 volts. Used for the analog
57
section.
1
S
Ground: Normally 0 volts. Tie to ground.
14
25
35
48
GND_TTL
9
S
TTL Ground: Normally 0 volts. Tie to ground.
40
GND_HS
18
S
Serial Output Ground: Normally 0 volts.
GND_A1
30
S
Analog Ground: Normally 0 volts.
GND_A2
56
Test Mode/No Connect Pins
TCLKENB
28
I-TTL
Enable External Serial Rate Clock Input: When set high, this input
causes the TXCLK input to be used for the serial transmit clock
rather than the internal VCO clock. It is intended for diagnostic
purposes and normally tied low.
NC
7
15
16
21
22
23
29
34
38
39
42
43
44
45
No Connect: These pins should be left unconnected.
17