HDMP-1032 Datasheet, PDF (11/32 Pages) Agilent(Hewlett-Packard) – 1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate

HDMP-1034 (Rx) Timing
The Rx timing diagram when
RXREADY=1 is shown in Figure
6. The serial data stream is
deserialized into a parallel word
at 1/20 the serial baud rate.
RXDATA, RXCNTL and RXDSLIP
are clocked out with the falling
edge of RXCLK1 and appear after
a delay of t_d. RXCLK1 and its
complement RXCLK0 are both
50% duty cycle clocks.
When the PASS system is dis-
abled (PASSENB=0), there is a
latency delay of two words from
the input of the first serial bit of a
word to the parallel outputs. The
parallel outputs, RX[0-15],
RXFLAG, RXREADY, RXERROR,
When the PASS system is enabled
(PASSENB=1), the timing of the
parallel word is adjusted auto-
matically ± 30% of the word pe-
riod so that it can be clocked out
with the rising edge of REFCLK
and appear after a delay of t_dp.
HDMP-1034 (Rx) Timing Characteristics
Tc = –20°C to +85°C, V_CC = 3.15V to 3.45V. Typical values are at Tc = 25°C, V_CC = 3.3V
Symbol Parameter
Unit
Min. Typ. Max.
t_d
Synchronous Output Delay referenced to the falling
nsec
0
2.0
3.5
edge of RXCLK1, PASS System Disabled (PASSENB=0).
t_dp
Synchronous Output Delay referenced to the rising
nsec
6.0
6.6
8.0
edge of REFCLK, PASS System Enabled (PASSENB=1).
t_sk
Allowable skew between HSIN and REFCLK before
PASS system resets, PASSENB=1.
nsec
20% word
period
-0.4 nsec
HSIN
WORD 1
WORD 2
WORD 3
WORD 4
W
C
W
C
W
C
W
C
BIT 0
RXCLK1
RXCLK0
REFCLK
Figure 6. HDMP-1034 (Rx) Timing Diagram.
11
RX[0]
t_d
t_dp
NOTE: W = 16 BIT WORD FIELD,
C = 4 BIT CODE FIELD