HDMP-1032 Datasheet, PDF (10/32 Pages) Agilent(Hewlett-Packard) – 1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate

HDMP-1032 (Tx) Timing
The Tx timing diagram is shown
in Figure 5. Under normal opera-
tions, the Tx PLL locks an inter-
nally generated clock to the
incoming TXCLK at which time
LOCKED is set high. The incom-
ing data, TX[0-15], TXDATA,
TXCNTL, and TXFLAG are
latched by this internal clock. The
data must be valid for t_s
before it is sampled and remain
valid for a time t_h after it is
sampled.
The setup and hold time param-
eters, t_s and t_h, are referenced to
the rising edge of TXCLK.
The start of a word, bit TX[0],
in the high speed serial output
occurs after a delay of t_d after
the rising edge of the TXCLK.
The typical value of t_d is
approximately one clock cycle.
HDMP-1032 (Tx) Timing Characteristics
Tc = –20°C to +85°C, V_CC = 3.15V to 3.45V
Symbol Parameter
t_s
Setup Time, for TX[0-15], TXDATA, TXCNTL and
TXFLAG Relative to Rising Edge of TXCLK.
t_h
Hold Time, for TX[0-15], TXDATA, TXCNTL and
TXFLAG Relative to Rising Edge of TXCLK.
Unit
Min.
Typ.
Max.
nsec
2.5
nsec
2.5
TXCLK
TX[0-15]
TXDATA
TXCNTL
TXFLAG
t_s
t_h
HSOUT
Figure 5. HDMP-1032 (Tx) Timing Diagram.
10
W-FIELD
t_d
C-FIELD