BC9824 Datasheet, PDF (9/22 Pages) Holtek Semiconductor Inc – Low Power High Performance Low Power High Performance

BC9824
Data and Control Interface
TX/RX FIFO
The data FIFOs are used to store payload that is to be
transmitted (TX FIFO) or payload that is received and
ready to be clocked out (RX FIFO). The FIFO is ac-
cessible in both PTX mode and PRX mode.
There are three levels 32 bytes FIFO for both TX and
RX, supporting both acknowledge mode or no ac-
knowledge mode with up to six pipes.
• TX three levels, 32 byte FIFO
• RX three levels, 32 byte FIFO
Both FIFOs have a controller and are accessible
through the SPI by using dedicated SPI commands. A
TX FIFO in PRX can store payload for ACK packets
to three different PTX devices. If the TX FIFO con-
tains more than one payload to a pipe, payloads are
handled using the first in first out principle. The TX
FIFO in a PRX is blocked if all pending payloads are
addressed to pipes where the link to the PTX is lost.
In this case, the MCU can flush the TX FIFO by using
the FLUSH_TX command.
The RX FIFO in PRX may contain payload from up
to three different PTX devices.
A TX FIFO in PTX can have up to three payloads
stored.
The TX FIFO can be written to by three commands,
W_TX_PAYLOAD and W_TX_PAYLOAD_NO_
ACK in PTX mode and W_ACK_PAYLOAD in PRX
mode. All three commands give access to the TX_
PLD register.
The RX FIFO can be read by the command R_RX_
PAYLOAD in both PTX and PRX mode. This com-
mand gives access to the RX_PLD register.
The payload in TX FIFO in a PTX is NOT removed if
the MAX_RT IRQ is asserted.
In the FIFO_STATUS register it is possible to read if
the TX and RX FIFO are full or empty. The TX_RE-
USE bit is also available in the FIFO_STATUS regis-
ter. TX_REUSE is set by the SPI command REUSE_
TX_PL, and is reset by the SPI command: W_TX_
PAYLOAD or FLUSH TX.
Interrupt
In BC9824 there is an active low interrupt (IRQ) pin,
which is activated when TX_DS IRQ, RX_DR IRQ
or MAX_RT IRQ are set high by the state machine in
the STATUS register. The IRQ pin resets when MCU
writes ‘1’ to the IRQ source bit in the STATUS regis-
ter. The IRQ mask in the CONFIG register is used to
select the IRQ sources that are allowed to assert the
IRQ pin. By setting one of the MASK bits high, the
corresponding IRQ source is disabled. By default all
IRQ sources are enabled.
The 3 bit pipe information in the STATUS register is
updated during the IRQ pin high to low transition. If
the STATUS register is read during an IRQ pin high
to low transition, the pipe information is unreliable.
SPI Interface
• SPI Command
The SPI commands are shown in the below table.
Every new command must be started by a high to
low transition on CSN.
In parallel to the SPI command word applied on the
MOSI pin, the STATUS register is shifted serially
out on the MISO pin.
The serial shifting SPI commands is in the follow-
ing format:
♦♦ _{<Command word: MSB bit to LSB bit (one}
byte)>
♦♦ _{<Data bytes: LSB byte to MSB byte, MSB bit}
in each byte first> for all registers at bank 0 and
register 9 to register 14 at bank 1
♦♦ _{<Data bytes: MSB byte to LSB byte, MSB bit in}
each byte first> for register 0 to register 8 at bank 1
Rev. 1.00
9
October 20, 2015