BC9824 Datasheet, PDF (11/22 Pages) Holtek Semiconductor Inc – Low Power High Performance Low Power High Performance

BC9824
• SPI Timing
SCK
CSN
Write to SPI register:
MOSI
x
C7 C6 C5 C4 C3 C2 C1 C0 x D7 D6 D5 D4 D3 D2 D1 D0 ^x
MISO HI-Z S7 S6 S5 S4 S3 S2 S1 S0
0
0 00 00 0 0
Hi-Z
MOSI
MISO
Read from SPI register:
x C7 C6 C5 C4 C3 C2 C1 C0
x
S7 S6 S5 S4 S3 S2 S1 S0
x
D7 D6 D5 D4 D3 D2 D1 D0 ^x
SPI Timing
Cn: SPI command bit
Sn: STATUS register bit
Dn: Data Bit (LSB byte to MSB byte, MSB bit in each byte first)
Note: The SPI timing is for bank 0 and register 9 to 14 at bank 1. For register 0 to 8 at bank 1, the byte order is
inversed that the MSB byte is R/W before LSB byte.
Tcwh
CSN
SCK
MOSI
Tcc
Tch
Tcl
Tdh
Tdc
C7
C6
Tcch
C0
MISO
Tcsd
Tcd
S7
Tcdz
S0
SPI NOP Timing Diagram
Symbol
Parameters
Min
Max
Tdc
Data to SCK Setup
10
Tdh
SCK to Data Hold
20
Tcsd
CSN to Data Valid
38
Tcd
SCK to Data Valid
55
Tcl
SCK Low Time
40
Tch
SCK High Time
40
Fsck
SCK Frequency
0
8
Tr,Tf
SCK Rise and Fall
100
Tcc
CSN to SCK Setup
2
Tcch
SCK to CSN Hold
2
Tcwh
CSN Inactive time
50
Tcdz
CSN to Output High Z
38
SPI Timing Parameter
Units
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
Rev. 1.00
11
October 20, 2015