BC9824 Datasheet, PDF (1/22 Pages) Holtek Semiconductor Inc – Low Power High Performance Low Power High Performance

BC9824
Low Power High Performance
2.4GHz GFSK Transceiver
Features
• 2400-2483.5MHz ISM band operation
• Support 250Kbps,1Mbps and 2Mbps air data rate
• Programmable output power
• Low power consumption
• Tolerate ± 60ppm 16MHz crystal
• Variable payload length from 1 to 32bytes
• Automatic packet processing
• 6 data pipes for 1:6 star networks
• 1.9V to 3.6V power supply
• 4-pin SPI interface with maximum 8MHz clock rate
• 20-pin QFN package
Applications
• Wireless PC peripherals
• Wireless mice and keyboards
• Wireless gamepads
• Wireless audio
• VOIP and wireless headsets
• Remote controls
• Consumer electronics
• Home automation
• Toys
• Personal health and entertainment
General Description
BC9824 is a GFSK transceiver operating in the world
wide ISM frequency band at 2400~2483.5 MHz. Burst
mode transmission and up to 2Mbps air data rate make
them suitable for applications requiring ultra low
power consumption. The embedded packet processing
engines enable their full operation with a very simple
MCU as a radio system. Auto re-transmission and
auto acknowledge give reliable link without any MCU
interference.
BC9824 operates in TDD mode, either as a transmitter
or as a receiver.
The RF channel frequency determines the center of
the channel used by BC9824. The frequency is set by
the RF_CH register in register bank 0 according to the
following formula: F0= 2400 + RF_CH (MHz). The
resolution of the RF channel frequency is 1MHz.
A transmitter and a receiver must be programmed
with the same RF channel frequency to be able to
communicate with each other.
The output power of BC9824 is set by the RF_PWR
bits in the RF_SETUP register.
Demodulation is done with embedded data slicer and
bit recovery logic. The air data rate can be programmed
to 250Kbps, 1Mbps or 2Mbps by RF_DR_HIGH and
RF_DR_LOW register. A transmitter and a receiver
must be programmed with the same setting.
In the following chapters, all registers are in register
bank 0 except with explicit claim.
Block Diagram
RFP
RFN
Integrated
TDD RF
Transceiver
FM
Demodulator
Data Slicer
Power
Management
FM
Modulator
Gaussian shaping
Rx FIFO
Packet
Processing &
State Control
Tx FIFO
SPI
Interface
Register
banks
CSN
SCK
MOSI
MISO
IRQ
CE
XTALP XTALN
Rev. 1.00
1
October 20, 2015