BC9824 Datasheet, PDF (16/22 Pages) Holtek Semiconductor Inc – Low Power High Performance Low Power High Performance

BC9824
Address
(Hex)
Mnemonic
N/A ACK_PLD
N/A TX_PLD
N/A RX_PLD
DYNPD
Reserved
DPL_P5
DPL_P4
1C _{DPL_P3}
DPL_P2
DPL_P1
DPL_P0
FEATURE
Reserved
1D EN_DPL
EN_ACK_PAY
EN_DYN_ACK
Bit
Reset
Value
255:0
X
255:0
X
255:0
X
7:6
0
5
0
4
0
3
0
2
0
1
0
0
0
7:3
0
2
0
1
0
0
0
Type
Description
Written by separate SPI command ACK packet payload to
data pipe number PPP given in SPI command
W Used in RX mode only
Maximum three ACK packet payloads can be pending.
Payloads with same PPP are handled first in first out.
Written by separate SPI command TX data pay-load
W
register 1 - 32 bytes. This register is implemented as a
FIFO with three levels.
Used in TX mode only
Read by separate SPI command
R
RX data payload register. 1 - 32 bytes.
This register is implemented as a FIFO with three levels.
All RX channels share the same FIFO.
Enable dynamic payload length
R/W Only ‘00’ allowed
R/W
Enable dynamic payload length data pipe 5.
(Requires EN_DPL and ENAA_P5)
R/W
Enable dynamic payload length data pipe 4.
(Requires EN_DPL and ENAA_P4)
R/W
Enable dynamic payload length data pipe 3.
(Requires EN_DPL and ENAA_P3)
R/W
Enable dynamic payload length data pipe 2.
(Requires EN_DPL and ENAA_P2)
R/W
Enable dynamic payload length data pipe 1.
(Requires EN_DPL and ENAA_P1)
R/W
Enable dynamic payload length data pipe 0.
(Requires EN_DPL and ENAA_P0)
R/W Feature Register
R/W Only ‘00000’ allowed
R/W Enables Dynamic Payload Length
R/W Enables Payload with ACK
R/W Enables the W_TX_PAYLOAD_NOACK command
Note: Don’t write reserved registers and registers at other addresses in register bank 0
Rev. 1.00
16
October 20, 2015