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BC9824 Datasheet, PDF (12/22 Pages) Holtek Semiconductor Inc – Low Power High Performance Low Power High Performance | |||
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BC9824
Register Map
There are two register banks, which can be toggled by SPI command âACTIVATEâ followed with 0x53 byte, and
bank status can be read from Bank0_REG7 [7].
Register Bank 0
Address
(Hex)
Mnemonic
Bit
CONFIG
Reserved
7
MASK_RX_DR 6
MASK_TX_DS
5
00 MASK_MAX_RT 4
EN_CRC
3
CRCO
2
PWR_UP
1
PRIM_RX
0
EN_AA
Reserved
7:6
ENAA_P5
5
ENAA_P4
4
01
ENAA_P3
3
ENAA_P2
2
ENAA_P1
1
ENAA_P0
0
EN_RXADDR
Reserved
7:6
ERX_P5
5
ERX_P4
4
02
ERX_P3
3
ERX_P2
2
ERX_P1
1
ERX_P0
0
SETUP_AW
Reserved
7:2
03
AW
1:0
Reset
Value
0
0
0
0
1
0
0
0
00
1
1
1
1
1
1
00
0
0
0
0
1
1
000000
11
Type
Description
Configuration Register
R/W Only '0' allowed
Mask interrupt caused by RX_DR
R/W 1: Interrupt not reflected on the IRQ pin
0: Reflect RX_DR as active low interrupt on the IRQ pin
Mask interrupt caused by TX_DS
R/W 1: Interrupt not reflected on the IRQ pin
0: Reflect TX_DS as active low interrupt on the IRQ pin
Mask interrupt caused by MAX_RT
R/W 1: Interrupt not reflected on the IRQ pin
0: Reflect MAX_RT as active low interrupt on the IRQ pin
R/W
Enable CRC. Forced high if one of the bits in the EN_AA is
high
CRC encoding scheme
R/W '0' - 1 byte
'1' - 2 bytes
R/W 1: POWER UP, 0:POWER DOWN
R/W
RX/TX control,
1: PRX, 0: PTX
Enable âAuto Acknowledgmentâ Function
R/W Only '00' allowed
R/W Enable auto acknowledgement data pipe 5
R/W Enable auto acknowledgement data pipe 4
R/W Enable auto acknowledgement data pipe 3
R/W Enable auto acknowledgement data pipe 2
R/W Enable auto acknowledgement data pipe 1
R/W Enable auto acknowledgement data pipe 0
Enabled RX Addresses
R/W Only '00' allowed
R/W Enable data pipe 5.
R/W Enable data pipe 4.
R/W Enable data pipe 3.
R/W Enable data pipe 2.
R/W Enable data pipe 1.
R/W Enable data pipe 0.
Setup of Address Widths
(common for all data pipes)
R/W Only '000000' allowed
RX/TX Address field width
'00' - Illegal
R/W
'01' - 3 bytes
'10' - 4 bytes
'11' - 5 bytes
LSB bytes are used if address width is below 5 bytes
Rev. 1.00
12
October 20, 2015
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