BC9824 Datasheet, PDF (13/22 Pages) Holtek Semiconductor Inc – Low Power High Performance Low Power High Performance

BC9824
Address
(Hex)
Mnemonic
SETUP_RETR
ARD
04
ARC
RF_CH
05 Reserved
RF_CH
RF_SETUP
Reserved
RF_DR_LOW
PLL_LOCK
RF_DR_HIGH
06
RF_PWR[1:0]
LNA_HCURR
STATUS
RBANK
RX_DR
07
MAX_RT
RX_P_NO
TX_FULL
Bit
Reset
Value
Type
Description
Setup of Automatic Retransmission
Auto Retransmission Delay
‘0000’ – Wait 250 us
‘0001’ – Wait 500 us
7:4
0000
R/W
‘0010’ – Wait 750 us
……..
‘1111’ – Wait 4000 us
(Delay defined from end of transmission to start of next
transmission)
Auto Retransmission Count
‘0000’ –Re-Transmit disabled
3:0 0011 R/W ‘0001’ – Up to 1 Re-Transmission on fail of AA
……
‘1111’ – Up to 15 Re-Transmission on fail of AA
RF Channel
7
0
R/W Only '0' allowed
6:0 0000010 R/W Sets the frequency channel
RF Setup Register
7:6
0
R/W Only '00' allowed
5
0
R/W Set Air Data Rate. See RF_DR_HIGH for encoding.
4
0
R/W Force PLL lock signal. Only used in test
Set Air Data Rate.
Encoding: RF_DR_LOW, RF_DR_HIGH:
3
1
R/W
‘00’ – 1Mbps
‘01’ – 2Mbps (default)
‘10’ –250Kbps
‘11’ – 2Mbps
Set RF output power in TX mode
RF_PWR[1:0]
2:1
11
R/W
'00' – -26 dBm
‘01’ – -14 dBm
‘10’ – -6 dBm
‘11’ – -1 dBm
Setup LNA gain
0
1
R/W 0:Low gain(20dB down)
1:High gain
Status Register (In parallel to the SPI command word
applied on the MOSI pin, the STATUS register is shifted
serially out on the MISO pin)
Register bank selection states. Switch register bank is
7
0
R
done by SPI command “ACTIVATE” followed by 0x53
0: Register bank 0
1: Register bank 1
Data Ready RX FIFO interrupt
6
0
R/W Asserted when new data arrives RX FIFO
Write 1 to clear bit.
Maximum number of TX retransmits interrupt
4
0
R/W Write 1 to clear bit. If MAX_RT is asserted it must be
cleared to enable further communication.
3:1
111
Data pipe number for the payload available for reading
from RX_FIFO
R 000-101: Data Pipe Number
110: Not used
111: RX FIFO Empty
TX FIFO full flag.
0
0
R 1: TX FIFO full
0: Available locations in TX FIFO
Rev. 1.00
13
October 20, 2015