HD66730 Datasheet, PDF (80/131 Pages) Hitachi Semiconductor – Dot-Matrix Liquid Crystal Display Controller/Driver Supporting Japanese Kanji, Korean Font Display

HD66730/HD66731
Reset Function
The HD66730/1 is reset by setting the RESET pin to low level. During reset, the system performs next-
control-register setting and executes instructions. The busy flag (BF) therefore indicates a busy state (BF =
1) at this time, which means that only the index register and status register can be accessed.
Display clear (DDRAM reset) is performed automatically by reset input. Since more than 1,000 clocks of
execution cycles are needed to initialize the DDRAM, the reset period must be set to more than this
number. Note that if the reset input conditions specified in Electrical Characteristics are not satisfied, the
HD66730/1 will not operate correctly, and reset should be performed by software.
Initialization of Instruction Register Function
1. Index Register: IR
The index register cannot be initialized by reset. After reset release, the index register must be set to
access a control register.
2. Status register: SR
BF = 1: Busy state
3. Entry mode register: R0
I/D = 1: +1 (incrementation)
RM1/0 = 00: DDRAM selection
4. Function set register: R1
BST = 0: Booster off
EXT2/1 = 11: Driver extension enable
DT1/0 = 11: 1/53 duty drive
DCL = 1: Display-clear execution
Note: At least 1,000 clock cycles of execution time is needed to clear the DDRAM.
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