HD66730 Datasheet, PDF(65/131 Page) Hitachi Semiconductor – Dot-Matrix Liquid Crystal Display Controller/Driver Supporting Japanese Kanji, Korean Font Display

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

HD66730 Datasheet, PDF (65/131 Pages) Hitachi Semiconductor – Dot-Matrix Liquid Crystal Display Controller/Driver Supporting Japanese Kanji, Korean Font Display

◁

HD66730/HD66731

Relationship between SEGRAM Addresses and Display Patterns

SEGRAM data is displayed when the select level of the COMS pin is output. Since SEGRAM data does

not depend on character code data in DDRAM, and does not undergo horizontal smooth scroll, it can be

used to display icon and marks. The following shows the relationship between SEGRAM addresses and

segment output pins.

Table 8 Relationship between SEGRAM Addresses and Display Patterns

SEGRAM

Address

A3 A2 A1 A0

0 000

0 001

0 010

0 011

0 100

0 101

0 110

0 111

1 000

1 001

1 010

1 011

1 100

1 101

1 110

1 111

D7 D6

B1 B0

SEGRAM Data

SEG1

SEG7

SEG13

SEG19

SEG25

SEG31

SEG37

SEG43

SEG49

SEG55

SEG61

SEG67

SEG73

SEG79

SEG85

SEG91

SEG2

SEG8

SEG14

SEG20

SEG26

SEG32

SEG38

SEG44

SEG50

SEG56

SEG62

SEG68

SEG74

SEG80

SEG86

SEG92

SEG3

SEG9

SEG15

SEG21

SEG27

SEG33

SEG39

SEG45

SEG51

SEG57

SEG63

SEG69

SEG75

SEG81

SEG87

SEG93

SEG4

SEG10

SEG16

SEG22

SEG28

SEG34

SEG40

SEG46

SEG52

SEG58

SEG64

SEG70

SEG76

SEG82

SEG88

SEG94

SEG5 SEG6

SEG11 SEG12

SEG17 SEG18

SEG23 SEG24

SEG29 SEG30

SEG35 SEG36

SEG41 SEG42

SEG47 SEG48

SEG53 SEG54

SEG59 SEG60

SEG65 SEG66

SEG71 SEG72

SEG77 SEG78

SEG83 SEG84

SEG89 SEG90

SEG95 SEG96

Blinking control

Pattern on/off

Notes: 1. SEG1 to SEG71 are pin numbers of the segment output driver of the HD66730. Pin SEG1 is

positioned on the left edge of the display. Segments from SEG72 on are displayed by extension

drivers. After SEG 96, display is performed from SEG1 again.

2. The lower six bits (D0 to D5) indicate display on/off for of each segment. A bit setting of 1 selects

display while 0 selects no display.

3. Pattern blinking of the lower six bits is controlled by the upper two bits (D6 and D7) of SEGRAM

data. When the upper two bits (B0 and B1) are 10, segments whose corresponding bits in the

lower 6 bits are set to 1 will blink on the display. When the upper two bits (B0 and B1) are 01,

only the bit-5 pattern can blink. Do not attempt to set the upper two bits (B0 and B1) to 11

(setting is prohibited).

▷