HD66730 Datasheet, PDF (16/131 Pages) Hitachi Semiconductor – Dot-Matrix Liquid Crystal Display Controller/Driver Supporting Japanese Kanji, Korean Font Display

HD66730/HD66731
Function Description
System Interface
The HD66730/1 has two system interfaces: a synchronized serial one and an 8-bit bus. Both are selected by
the IM pin.
The HD66730/1 has five types of 8-bit registers: an index register (IDR), status register (STR), various
control registers, RAM address register (RAR), and RAM data register (RDR).
The index register (IDR) selects control registers, the RAM address register (RAR) or the RAM data
register (RDR) for performing data transfer.
The status register (STR) indicates the internal state of the system. Various control registers store display
control data here.
The RAM address register (RAR) stores the address data of display data RAM (DDRAM), character
generator RAM (CGRAM), and segment RAM (SEGRAM).
The RAM data register (RDR) temporarily stores data to be written into DDRAM, CGRAM, or SEGRAM.
Data written into the RDR from the MPU is automatically written into DDRAM, CGRAM, or SEGRAM
by internal operations. The RDR is also used for data storage when reading data from DDRAM, CGRAM,
or SEGRAM. Here, when address information is written into the RAR, data is read and then stored into the
RDR from DDRAM, CGRAM, or SEGRAM by internal operations.
Data transfer between the MPU is then completed when the MPU reads the RDR. After this read, data in
DDRAM, CGRAM, or SEGRAM stored at the next address is sent to the RDR at the next data read from
the MPU.
These registers can be selected by the register select signal (RS) and the read/write signal (R/W) in the 8-bit
bus interface, and by the RS bit and R/W bit of start-byte data in the synchronized serial interface.
Busy Flag
When the busy flag is 1, the HD66730/1 is in internal operation mode, and only the status register (STR)
can be accessed. The busy flag (BF) is output from bit 7 (DB7). Access of other registers can be performed
only after confirming that the busy flag is 0.
RAM Address Counter (RAR)
The RAM address counter (RAR) provides addresses for accessing DDRAM, CGRAM, or SEGRAM.
When an initial address value is written into the RAM counter (RAR), the RAR is automatically
incremented or decremented by 1. Note that a control register specifies which RAM (DDRAM, CGRAM,
SEGRAM) to select.
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