HD66730 Datasheet, PDF (75/131 Pages) Hitachi Semiconductor – Dot-Matrix Liquid Crystal Display Controller/Driver Supporting Japanese Kanji, Korean Font Display

HD66730/HD66731
Scroll Control Register 3 (R7)
The scroll control register 3 (Figure 14) includes bits SQ5, SQ4, SQ3, SQ2, SQ1, and SQ0.
SQ0 to SQ5: These bits designate the number of dots to be horizontally scrolled to the left on the panel.
Horizontal smooth scroll can be performed for any number of dots between 1 and 48 inclusive by using the
non-display DDRAM area. When these bits are 000000, scrolling is not performed. When these bits are
110000, 48 dots are scrolled to the left. If these bits are set to a value above 110000, 48 dots are still
scrolled. Refer to Horizontal Smooth Scroll for details.
RAM Address Register (R8)
The RAM address register (Figure15) initially contains the RAM address at which incrementation
(decrementation) starts. RAM selection bits (RM1/0) in the entry mode register (R0) select which RAM to
access (DDRAM/CGRAM/SEGRAM). When DDRAM (RM1/0 = 00) is selected, address allocation differs
according to the number of display lines, but in all cases the most significant bit (RA7) is ignored. During a
1-line display (NL1/0 = 00), addresses H'00 to H'4F are allocated to that line. During a 2-line display,
addresses H'00 to H'27 are allocated to the first line, and addresses H'40 to H'67 are allocated to the second
line. During a 4-line display, addresses H'00 to H'13 are allocated to the first line, H'20 to H'33 to the
second , H'40 to H'53 to the third, and H'60 to H'73 to the fourth. See Table 14.
When CGRAM (RM1/0 = 10) is selected, addresses H'00 to H'19 are allocated to the first character and
addresses H'20 to H'39 are allocated to the second character, and so on (Table 15). The setting of addresses
between characters (example: H'1A to H'1F) is ignored here. When SEGRAM is selected (RM1/0 = 11),
addresses H'0 to H'F are allocated to the RAM and the upper four bits (R4 to R7) are ignored (Table 16).
R/W RS DB7
DB0
0 1 0 0 SQ5 SQ4 SQ3 SQ2 SQ1 SQ0
Figure 14 Scroll Control Register 3
R/W RS DB7
DB0
0 1 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
Figure 15 RAM Address Register
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