HD404618 Datasheet, PDF (60/89 Pages) Hitachi Semiconductor – 4-Bit Single-Chip Microcomputer

HD404618 Series
Table 29 LCD Frame Periods for Different Duties
Static Duty LMR
Instruction Bit 3
cycle time 0
Bit 2
0
Bit 3
0
Bit 2
1
Bit 3
1
Bit 2
0
Bit 3
1
Bit 2
1
CL0
CL1
CL2
CL3*
10 µs
512 Hz
390.6 Hz
48.8 Hz
24.4 Hz/64 Hz
5 µs
512 Hz
781.2 Hz
97.6 Hz
48.8 Hz/64 Hz
1/2 Duty
LMR
Instruction Bit 3
cycle time 0
Bit 2
0
Bit 3
0
Bit 2
1
Bit 3
1
Bit 2
0
Bit 3
1
Bit 2
1
CL0
CL1
CL2
CL3*
10 µs
256 Hz
195.3 Hz
24.4 Hz
12.2 Hz/32 Hz
5 µs
256 Hz
390.6 Hz
48.8 Hz
24.4 Hz/32 Hz
1/3 Duty
LMR
Instruction Bit 3
cycle time 0
Bit 2
0
Bit 3
0
Bit 2
1
Bit 3
1
Bit 2
0
Bit 3
1
Bit 2
1
CL0
CL1
CL2
CL3*
10 µs
170.6 Hz
130.2 Hz
16.3 Hz
8.1 Hz/21.3 Hz
5 µs
170.6 Hz
260.4 Hz
32.6 Hz
16.2 Hz/21.3 Hz
1/4 Duty
LMR
Instruction Bit 3
cycle time 0
Bit 2
0
Bit 3
0
Bit 2
1
Bit 3
1
Bit 2
0
Bit 3
1
Bit 2
1
CL0
CL1
CL2
CL3*
10 µs
128 Hz
97.7 Hz
12.2 Hz
6.1 Hz/16 Hz
5 µs
128 Hz
195.4 Hz
24.4 Hz
12.2 Hz/16 Hz
Note:
* The division ratio depends on the value of bit 3 of timer mode register A (TMA3): The first value is
for TMA3 = 0 and the second is for TMA3 = 1.
When TMA3 = 0, CL3 = f_cyc × duty cycle/4096.
When TMA3 = 1, CL3 = 32.768 kHz × duty cycle/512
60