HD404618 Datasheet, PDF (45/89 Pages) Hitachi Semiconductor – 4-Bit Single-Chip Microcomputer

HD404618 Series
Timer B interrupt
request flag
(IFTB)
Selector
INT₁
System ^fcyc/fSUB
clock _{(tcyc/tsubcyc)}
Prescaler S (PSS)
Timer counter register BU (TCBU)
Clock
Timer counter
register BL
(TCBL)
Timer counter B
(TCB)
Overflow
Timer load
register BU
(TLRU)
Free-running
control
Timer load
register BL
(TLRL)
3
Timer mode
register B
(TMB)
Figure 27 Timer B Block Diagram
Timer C (TCCL and TCRL: $00E, TCCU and TCRU: $00F): Eight-bit write-only timer load register
(TCRL and TCRU) and read-only timer counter (TCCL and TCCU) located at the same addresses. The
eight-bit configuration consists of lower and upper 4-bit digits located at sequential addresses. The
operation of timer C is basically the same as that of timer B.
The auto-reload function and prescaler division ratio of timer C depend on the state of timer mode register
C (TMC). Timer C is initialized to the value set in TMC by software, and is then incremented by one at
each clock input. If an input is applied to timer C after it has reached $FF, an overflow is generated. In
this case, if the auto-reload function is enabled, timer C is initialized to its initial value; if auto-reload is
disabled, the timer is initialized to $00. The overflow sets the timer C interrupt request flag (IFTC: $002,
bit 2).
Timer C also functions as a watchdog timer. If a program routine runs out of control and an overflow is
generated while the watchdog on (WDON) flag is set, the MCU is reset. This error can be detected by
having the program control timer C reset before timer C reaches $FF.
The WDON can only have 1 written to it ; it is cleared to 0 only by MCU reset.
Timer Mode Register A (TMA: $008): Four-bit write-only register that controls timer A as shown in
table 21.
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