HD404618 Datasheet, PDF (58/89 Pages) Hitachi Semiconductor – 4-Bit Single-Chip Microcomputer

HD404618 Series
Table 27 LCD Control Register
LCR
LCR
LCR
Bit 2
Display in
Watch Mode or
Subactive Mode Bit 1
Power Switch
On/Off
Bit 0
Blank/Display
0
Off
0
Off
0
Blank
1
On
1
On
1
Display
Note: When using an LCD in watch mode or subactive mode, use the divided output of a 32-kHz oscillator
as the LCD clock and set bit 2 of the LCR to 1. If using the divided output of the system clock as the
LCD clock, always set bit 2 of the LCR to 0.
LCD Duty/Clock Control Register (LMR: $014): Four-bit write-only register which selects the display
duty and LCD clock source, as shown in table 28.
Table 28 LCD Duty/Clock Control Register
LMR
Bit 3
Bit 2
Bit 1 Bit 0
Duty Selection/Input Clock Selection
—
—
0
0
1/4 duty cycle
—
—
0
1
1/3 duty cycle
—
—
1
0
1/2 duty cycle
—
—
1
1
Static
0
0
—
—
CL0 (32.768/64 kHz when using 32.768-kHz oscillator)
0
1
—
—
CL1 (f_cyc/256)
1
0
—
—
CL2 (f_cyc/2048)
1
1
—
—
CL3 (refer to table 29)
Note: f_cyc is the divided system clock output.
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