HD404618 Datasheet, PDF (54/89 Pages) Hitachi Semiconductor – 4-Bit Single-Chip Microcomputer

HD404618 Series
During transmission, the input of eight clocks or the execution of the STS instruction sets the octal counter
to 000, and the serial interface enters transmit clock wait state. If the state changes from transmit to another
state, the serial interrupt request flag is set by the octal counter reaching 000.
STS instruction wait state
octal counter = 000
transmit clock disabled
Transmit clock wait state
(octal counter = 000)
Transmit clock
8 transmit clocks (external clock)
STS instruction
(IFS ^← 1)
Transfer state
(octal counter ≠ 000)
Figure 33 Serial Interface Mode Transitions
In this state, if the internal clock has been selected, the transmit clock is output in answer to the execution
of the STS instruction, but serial transmission is inhibited after the eighth clock is output.
If port mode register A (PMRA) is written to in transmit clock wait state or during transmission, the serial
mode register (SMR) must be written to, to initialize the serial interface. The serial interface then enters
STS wait state.
If the serial interface shifts from transfer state to another state, the octal counter returns to 000, setting the
serial interrupt request flag.
Transmit Clock Error Detection: The serial interface will malfunction if a spurious pulse caused by
external noise conflicts with a normal transmit clock during transmission. A transmit clock error of this
type can be detected as shown in figure 34.
If more than eight transmit clocks are input in transmit clock wait state, the serial interface state changes to
transfer, transmit clock wait, then back to transfer.
If the serial interface is set to STS wait state by writing data to the SMR after the serial interrupt request
flag has been reset, the flag is set again.
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