HD404618 Datasheet, PDF (47/89 Pages) Hitachi Semiconductor – 4-Bit Single-Chip Microcomputer

HD404618 Series
Table 21 Timer Mode Register A
TMA
Bit 3 Bit 2 Bit 1 Bit 0 Source Prescaler, Input Clock Period,
Operating Mode
0
0
0
0
PSS, 2048 t_cyc
1
PSS, 1024 t_cyc
1
0
PSS, 512 t_cyc
1
PSS, 128 t_cyc
1
0
0
PSS, 32 t_cyc
1
PSS, 8 t_cyc
1
0
PSS, 4 t_cyc
1
PSS, 2 t_cyc
1
0
0
0
PSW, 32 t_subcyc
1
PSW, 16 t_subcyc
1
0
PSW, 8 t_subcyc
1
PSW, 2 t_subcyc
1
0
0
PSW, 1/2 t_subcyc
1
Not used
Timer A mode
Time-base mode
1
0
PSW, TCA reset
1
Notes: 1. t_subcyc = 244.14 µs (when 32.768-kHz crystal oscillator is used)
2. Timer counter overflow output period(s) = input clock period(s) × 256
3. If PSW or TCA reset is selected while the LCD is operating, LCD operation halts (power switch
goes off).
When LCD is connected for display, the PSW and TCA reset periods must be set in the program
to the minimum.
4. In time base mode, the timer counter overflow output cycle must be greater than half of the
interrupt frame period (T/2 = t_RC).
If 1/2 t_subcyc is selected, t_RC must be 7.8125 ms ((MIS1, MIS0) = (0, 1), see figure 14).
5. The division ratio must not be modified during time-base mode operation, otherwise an overflow
cycle error will occur.
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