HD404618 Datasheet, PDF (44/89 Pages) Hitachi Semiconductor – 4-Bit Single-Chip Microcomputer

HD404618 Series
Timer B (TCBL and TLRL: $00A, TCBU and TLRU: $00B): Eight-bit write-only timer load register
(TLRL and TLRU) and read-only timer counter (TCBL and TCBU) located at the same addresses. The
eight-bit configuration consists of lower and upper 4-bit digits located at sequential addresses. A block
diagram of timer B is shown in figure 27.
Timer counter B is initialized by writing to timer load register B (TLR). In this case, the lower digit must
be written to first. The contents of TLR are loaded into the timer counter at the same time the upper digit is
written to, initializing the timer counter. TLR is initialized to $00 by MCU reset.
The count of timer B is obtained by reading timer counter B. In this case, the upper digit must be read first;
the count is latched when the upper digit is read.
An auto-reload function, input clock source, and prescaler division ratio of timer B depend on the state of
timer mode register B (TMB). When an external event input is used as the input clock source of TMB, the
R3₃/INT₁ pin must be set to INT₁ by setting port mode register A (PMRA: $004).
Timer B is initialized to the value set in TMB by software, and is then incremented by one each clock
input. If an input is applied to timer B after it has reached $FF, an overflow is generated. In this case, if
the auto-reload function is enabled, timer B is initialized to its initial value; if auto-reload is disabled, the
timer is initialized to $00. The overflow sets the timer B interrupt request flag (IFTB: $002, bit 0).
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