HD66712 Datasheet, PDF (46/88 Pages) Hitachi Semiconductor – Dot-Matrix Liquid Crystal Display Controller/Driver

HD66712U
Set DDRAM Address
A DDRAM address can be set while the RE bit is cleared to 0. Set DDRAM address sets the DDRAM
address binary AAAAAAA into the address counter.
After this address set, data is written to or read from the MPU for DDRAM.
However, when N and NW is 0 (1-line display), AAAAAAA can be (00)H to (4F)H. When N is 1 and
NW is 0 (2-line display), AAAAAAA is (00)H to (27)H for the first line, and (40)H to (67)H for the
second line. When NW is 1 (4-line display), AAAAAAA is (00)H to (13)H for the first line, (20)H to
(33)H for the second line, (40)H to (53)H for the third line, and (60)H to (73)H for the fourth line.
Set Scroll Quantity
When extended registor enable bit (RE) is 1, HDS5 to HDS0 can be set.
HDS5 to HDS0 specifies horizontal scroll quantity to the left of the display in dot units. The HD66712
uses the unused DDRAM area to execute a desired horizontal smooth scroll from 1 to 48 dots.
Note:
When performing a horizontal scroll as described above by connecting an extended driver, the
maximum number of characters per line decreases by the quantity set by the above horizontal
scroll. For example, when the maximum 24-dot scroll quantity (4 characters) is used with 6-dot
font width and 4-line display, the maximum numbers of characters is 20 – 4 = 16. Notice that in
low power mode (LP = 1), display shift and scroll cannot be performed.
Read Busy Flag and Address
Read busy flag and address reads the busy flag (BF) indicating that the system is now internally operating
on a previously received instruction. If BF is 1, the internal operation is in progress. The next instruction
will not be accepted until BF is reset to 0. Check the BF status before the next write operation. At the
same time, the value of the address counter in binary AAAAAAA is read out. This address counter is
used by both CG, DD, and SEGRAM addresses, and its value is determined by the previous instruction.
The address contents are the same as for CGRAM, DDRAM, and SEGRAM address set instructions.
Write Data to CG, DD, or SEGRAM
This instruction writes 8-bit binary data DDDDDDDD to CG, DD or SEGRAM. CG, DD or SEGRAM is
selected by the previous specification of the address set instruction (CGRAM address set / DDRAM
address set / SEGRAM address set). After a write, the address is automatically incremented or
decremented by 1 according to the entry mode. The entry mode also determines the display shift
direction.
409