HD66712 Datasheet, PDF (37/88 Pages) Hitachi Semiconductor – Dot-Matrix Liquid Crystal Display Controller/Driver

HD66712U
Transferring Serial Data
When the IM pin (interface mode) is low, the HD66712 enters serial interface mode. A three-line clock-
synchronous transfer method is used. The HD66712 receives serial input data (SID) and transmits serial
output data (SOD) by synchronizing with a transfer clock (SCLK) sent from the master side.
When the HD66712 interfaces with several chips, chip select pin (CS*) must be used. The transfer clock
(SCLK) input is activated by making chip select (CS*) low. In addition, the transfer counter of the
HD66712 can be reset and serial transfer synchronized by making chip select (CS*) high.
Here, since the data which was being sent at reset is cleared, restart the transfer from the first bit of this
data. In the case of a minimum 1 to 1 transfer system with the HD66712 used as a receiver only, an
interface can be established by the transfer clock (SCLK) and serial input data (SID). In this case, chip
select (CS*) should be fixed to low.
The transfer clock (SCLK) is independent from operational clock (CLK) of the HD66712. However,
when several instructions are continuously transferred, the instruction execution time determined by the
operational clock (CLK) (see continuous transfer) must be considered since the HD66712 does not have
an internal transmit/receive buffer.
To begin with, transfer the start byte. By receiving five consecutive bits (synchronizing bit string) at the
: ^{beginning of the start byte, the transfer counter of the HD66712 is reset and serial transfer is}
synchronized. The 2 bits following the synchronizing bit string (5 bits) specify transfer direction (R/
bit) and register select (RS bit). Be sure to transfer 0 in the 8th bit.
After receiving the start byte, instructions are received and the data/busy flag is transmitted. When the
transfer direction and register select remain the same, data can be continuously transmitted or received.
The transfer protocol is described in detail below.
• Receiving (write)
: After receiving the start synchronization bits, the R/ bit (= 0), and the RS bit with the start byte, an
8-bit instruction is received in 2 bytes: the lower 4 bits of the instruction are placed in the LSB of the
: ^{first byte, and the higher 4 bits of the instruction are placed in the LSB of the second byte. Be sure to}
transfer 0 in the following 4 bits of each byte. When instructions are continuously received with R/
bit and RS bit unchanged, continuous transfer is possible (see “Continuous Transfer” below).
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