HD66503 Datasheet, PDF (4/27 Pages) Hitachi Semiconductor – (240-Channel Common Driver with Internal LCD Timing Circuit)

HD66503
Classi-
fication
Control
signals
Symbol
CR, R, C
5(6(7
LCD
CL1
timing
FLM
M
Pin No.
247
248
249
261
Pin Name
CR
R
C
Reset
263
Clock 1
264
First line
marker
262
M
I/O
Input
I/O
I/O
I/O
Number
of Pins Functions
3
These pins are used as shown in Figure
4 in master mode, and as shown in
Figure 5 in slave mode.
1
The following initiation will be proceeded
by setting to initiation.
1) Stops the internal oscillator or the
external oscillator clock input.
2) Initializes the counters of the liquid
crystal display timing generator and
alternating signal (M) generator.
3) Set display off control output ('2&)
to low and turns off display.
After reset, display off control output
('2&) will stay low for four more frame
cycles (four clocks of FLM signals) to
prevent error display at initiation. The
electrical characteristics are shown in
Table 4. See Figure 2.
However, when reset is performed
during operation, RAM data in the
HD66520 which is used together with
the HD66503 may be destroyed.
Therefore, write data to the RAM again.
1
The bidirectional shift register shifts
data at the falling edge of CL1. During
master mode, this pin-outputs a data
transfer clock with a two times larger
cycle than the internal oscillator (or the
cycle of the external clock) with a duty
of 50%. During slave mode, this pin
inputs the external data transfer clock.
1
During master mode, pin FLM outputs
the first line marker. During slave mode,
this pin inputs the external data first line
marker. The shift direction of the first
line marker is determined by DUTY and
SHL signal as follows. Set signal DUTY
to high during slave mode. See Table 5.
1
Pin M inputs and outputs the alternating
signal of the LCD output.
930