HD66503 Datasheet, PDF (11/27 Pages) Hitachi Semiconductor – (240-Channel Common Driver with Internal LCD Timing Circuit)

HD66503
Internal Function Description
1. Generation of Signals CL1 and FLM: Signal CL1 shifts the scanning signal of the common driver. It
is a 50% duty-ratio clock that changes level synchronously with the rising edge of oscillator clock
CR.
FLM is a clock signal that is output once every 240 CL1 clock cycles for a duty of 1/240 (DUTY =
V_CC), and every 120 CL1 clock cycles for a duty of 1/120 (DUTY = GND).
2. Generation of Signal M: Signal M alternates current in the LCD. It alternates the current to decrease
cross talk after a certain number of lines ranging from 2 to 63 lines. The number of lines can be
specified with pins MWS0 to MWS5 by setting each pin to either V_CC or GND (H or L). In addition,
when pin MEOR is connected to GND, signal M is a simple line alternating waveform, and when pin
MEOR is connected to V_CC, signal M is an EOR (exclusive OR) of line alternating waveform and
frame alternating waveform.
CR
CL1
240
1
2
(120)
FLM
Figure 6 Generation of Signals CL1 and FLM
(When MWS0 to MWS5 = 6)
CL1
1
2
3
4
5
6
1
2
M
(MEOR = GND)
M
(MEOR = V_CC)
FLM
Figure 7 Generation of Signal M
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