HD66503 Datasheet, PDF (3/27 Pages) Hitachi Semiconductor – (240-Channel Common Driver with Internal LCD Timing Circuit)

HD66503
Pin Description
Classi-
fication
Power
supply
Symbol
V_CC1,
V_CC2
GND
V_EEL,
V_EER
V1L, R
V2L, R
V5L, R
V6L, R
Control M/6
signals
Pin No. Pin Name I/O
246
V_CC
267
Power
supply
250
GND
Power
supply
245
V_EE
268
Power
supply
244
V1
269
241
V2
272
242
V5
271
243
V6
270
Input
Input
Input
Input
266
Master/slave Input
DUTY
259
Duty
Input
MWS0 to 257
MWS5 256
255
254
253
252
MEOR 258
MWS0
MWS1
MWS2
MWS3
MWS4
MWS5
Input
M Exclusive- Input
OR
Number
of Pins Functions
2
V_CC–GND: logic power supply
1
2
V_CC–V_EE: LCD drive circuits power supply
2
LCD drive level power supply
See Figure 1.
2
2
2
1
Controls the initiation and termination of
the LCD timing generator. In addition,
the input/output is determined of 4 signal
pins: display data transfer clock (CL1);
first line marker (FLM); alternating signal
(M); and display off control ('2&). See
Table 1 for details.
1
Selects the display duty cycle.
Low level: 1/120 display duty ratio
High level:
1/240 display duty ratio
6
The number of line in the line alternating
waveform is set during master mode.
The number of lines can be set between
10 and 63.
When using the external alternating
signal or during slave mode, set the
number of lines to 0. See Table 2.
1
During master mode, the signals
alternating waveform output from pin M
is selected.
During low level, the line alternating
waveform is output from pin M.
During high level, pin M outputs an
EOR (exclusive OR) waveform between
a line alternating waveform and frame
alternating waveform. Set the pin to low
during slave mode. See Table 3.
929