MB84VD2008 Datasheet, PDF (9/30 Pages) Fujitsu Component Limited. – 8M (x 16) FLASH MEMORY & 2M (x 16) STATIC RAM

MB84VD2008-10/MB84VD2009-10
Table 7 Flash Memory Command Definitions
Com-
mand
Sequence
Bus
Write
Cycles
Req’d
First Bus Second Bus
Write Cycle Write Cycle
Addr. Data Addr. Data
Third Bus
Write Cycle
Addr. Data
Fourth Bus
Read/Write
Cycle
Addr. Data
Fifth Bus
Write Cycle
Addr. Data
Sixth Bus
Write Cycle
Addr. Data
Read/Reset 1 XXXH F0H — — — — — — — — — —
Read/Reset 3 555H AAH 2AAH 55H 555H F0H RA RD — — — —
Autoselect
3
555H
AAH 2AAH
55H
(BA)
555H
90H
—
—
—
—
—
—
Program
4 555H AAH 2AAH 55H 555H A0H PA PD — — — —
Chip Erase
6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H
Sector Erase 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA 30H
Erase
Suspend
1
BA B0H — — — — — — — — — —
Erase
Resume
1 BA 30H — — — — — — — — — —
Set to
Fast Mode
3 555H AAH 2AAH 55H 555H 20H — — — — — —
Fast
Program *
2 XXXH A0H PA PD — — — — — — — —
Reset from
Fast Mode *
2
BA 90H XXXH F0H — — — — — — — —
Extended
Sector
Protect
4 XXXH 60H SPA 60H SPA 40H SPA SD — — — —
Notes: 1. Address bits A11 to A18 = X = “H” or “L” for all address commands except or Program Address (PA), Sector
Address (SA), and Bank Address (BA).
2. Bus operations are defined in Tables 2 and 3.
3. RA = Address of the memory location to be read
PA = Address of the memory location to be programmed
Addresses are latched on the falling edge of the write pulse.
SA = Address of the sector to be erased. The combination of A18, A17, A16, A15, A14, A13, and A12 will
uniquely select any sector.
BA = Bank Address (A16 to A18)
4. RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the falling edge of write pulse.
5. SPA =Sector address to be protected. Set sector address (SA) and (A6, A1, A0) = (0, 1, 0).
SD = Sector protection verify data. Output 01H at protected sector addresses and output 00H at
unprotected sector addresses.
* : This command is valid while Fast Mode.
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