MB84VD2008 Datasheet, PDF (24/30 Pages) Fujitsu Component Limited. – 8M (x 16) FLASH MEMORY & 2M (x 16) STATIC RAM

MB84VD2008-10/MB84VD2009-10
• Write Cycle (SRAM)
Parameter
Symbol
Parameter Description
tWC
Write Cycle Time
tWP
Write Pulse Width
tCW
Chip Enable to End of Write
tBW
UB, LB Valid to End of Write
tAS
Address Setup Time
tWR
Write Recovery Time
tODW WE Low to Output High-Z
tOEW WE High to Output Active
tDS
Data Setup Time
tDH
Data Hold Time
• Write Cycle (Note 4) (WE control) (SRAM)
tWC
ADDRESSES
tAS
tWP
WE
Min.
85
60
75
55
0
0
—
0
35
0
Max.
Unit
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
35
ns
—
ns
—
ns
—
ns
tWR
tCW
CEs
UB, LB
tBW
tODW
tOEW
DOUT
Note 2
tDS
tDH
Note 3
DIN
Note 5
VALID DATA IN
Note 5
Notes: 2. If CEs goes LOW coincident with or after WE goes LOW, the output will remain at high
impedance.
3. If CEs goes HIGH coincident with or before WE goes HIGH, the output will remain at
high impedance.
4. If OE is HIGH during the write cycle, the outputs will remain at high impedance.
5. Because I/O signals may be in the output state at this Time, input signals of reverse
polarity must not be applied.
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