MB84VP24491HK Datasheet, PDF (48/70 Pages) Fujitsu Component Limited. – 128M (X16) FLASH MEMORY 32M (X16) Mobile FCRAMTM

MB84VP24491HK-70
• WRITE OPERATION (32M Page mode FCRAM)
Parameter
Symbol
Value
Min
Max
Unit Remarks
Write Cycle Time
tWC
70
Address Setup Time
tAS
0
CE1r Write Pulse Width
tCW
45
WE Write Pulse Width
tWP
45
LB / UB Write Pulse Width
tBW
45
CE1r Write Recovery Time
tWRC
15
WE Write Recovery Time
tWR
15
LB / UB Write Recovery Time
tBR
15
Data Setup Time
tDS
20
Data Hold Time
tDH
0
Address Invalid Time after Write
tAXW
—
OE High to CE1r Low Setup Time for
Write
tOHCL
–5
OE High to Address Setup Time
for Write
tOES
0
LB and UB Write Pulse Overlap
tBWO
20
CE1r High Pulse Width
tCP
15
1000
—
—
—
—
—
1000
1000
—
—
10
—
—
—
—
ns *1, *2
ns
*2
ns
*3
ns
*3
ns
*3
ns
*4
ns
*4
ns
*4
ns
ns
ns
*5
ns
*6
ns
*7
ns
ns
*1 : Maximum value is applicable if CE1r is kept at Low without any address change. If the relaxation is needed by
system operation, please contact local FUJITSU representative for the relaxation of 1 µs limitation.
*2 : Minimum value must be equal or greater than the sum of write pulse (tCW, tWP or tBW) and write recovery time
(tWRC, tWR or tBR).
*3 : Write pulse is defined from High to Low transition of CE1r, WE, or LB / UB, whichever occurs last.
*4 : Write recovery is defined from Low to High transition of CE1r, WE, or LB / UB, whichever occurs first.
*5 : Applicable to any address change when CE1r stays Low.
*6 : If OE is Low after minimum tOHCL, read cycle is initiated. In other word, OE must be brought to High within 5ns
after CE1r is brought to Low. Once read cycle is initiated, new write pulse should be input after minimum tRC
is met.
*7 : If OE is Low after new address input, read cycle is initiated. In other word, OE must be brought to High at the
same time or before new address valid. Once read cycle is initiated, new write pulse should be input after
minimum tRC is met.
47