MB84VP24491HK Datasheet, PDF (3/70 Pages) Fujitsu Component Limited. – 128M (X16) FLASH MEMORY 32M (X16) Mobile FCRAMTM

MB84VP24491HK-70
(Continued)
— FLASH MEMORY
• 0.13 µm Process Technology
• Dual Chip Enable (CE0f, CE1f)
CE0f controls 64M bits (Bank A and Bank B) region and CE1f controls 64M bits (Bank C and Bank D) bits region.
• Single 3.0 V Read, Program and Ease
Minimized system level power requirements
• Simultaneous Read/Write Operations (Dual Bank)
• FlexBank^TM *¹
Bank A(CE0f): 16 Mbit (4 KW ×8 and 32 KW ×31)
Bank B(CE0f): 48 Mbit (32 KW ×96)
Bank C(CE1f): 48 Mbit (32 KW ×96)
Bank D(CE1f): 16 Mbit (4 KW ×8 and 32 KW ×31)
• High Performance Page Mode
20 ns maximum page access time (70 ns random access time)
• 8 words Page Access Capability
• Minimum 100,000 Program/Erase Cycles
• Sector Erase Architecture
Eight 4 Kwords, two hundred fifty-four 32 Kwords, eight 8 Kwords sectors.
Any combination of sectors can be concurrently erased. Also supports full chip erase
• Dual Boot Block
Sixteen 4Kwords boot block sectors, eight at the top of the address range and eight at the bottom of the address
range
• HiddenROM Region
256 byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC Input Pin
At VIL, allows protection of “outermost” 2×4 K words on both ends of boot sectors, regardless of sector pro-
tection/unprotection status
At VIH, allows removal of boot sector protection
At VACC, increases program performance
• Embedded Erase^TM *² Algorithms
Automatically preprograms and erases the chip or any sector
• Embedded Program^TM *² Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion
• Ready/Busy Output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic Sleep Mode
When addresses remain stable, the device automatically switches itself to low power mode
• Low VCC Write Inhibit ≤ 2.5 V
• Program Suspend/Resume
Suspends the program operation to allow a read in another byte
• Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Hardware Reset Pin (RESET)
Hardware method to reset the device for reading array data
(Continued)
2