MB15U36 Datasheet, PDF (3/23 Pages) Fujitsu Component Limited. – Dual PLL Frequency Synthesizer with On-Chip Prescaler

Dual PLL Frequency Synthesizer with On-Chip Prescaler
Pin Descriptions: MB15U36
Pin No.
SSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin Name
Vcc₁
Vp₁
Do₁
GND1
fin₁
Xfin₁
GND1
OSC_IN
OSC_OUT
LD/f_OUT
Clock
Data
LE
GND2
Xfin₂
fin₂
GND2
Do₂
Vp₂
Vcc₂
I/O
Descriptions
–
Power supply voltage input pin for the RF1-PLL section, the shift register, and the oscillator input buffer. When poweris OFF, latched data
for RF1-PLL is lost.
I Power supply for the RF1-PLL charge pump. (Independent of pin 19)
O Charge pump output for the RF1-PLL section. Phase detector characteristics can be reversed using the FC-bit.
– Ground for the RF1-PLL section.
I Prescaler input for the RF1-PLL. Connection to an external VCO should be via AC coupling.
I Prescaler complimentary input for the RF1-PLL section. This pin should be grounded via a small capacitor.
– Ground for the RF1-PLL section.
I External TCXO reference oscillator input or connection to crystal. TCXO should be connected via AC coupling.
O Oscillator output or connection to crystal.
O
Lock detect signal output (LD) or phase comparator monitoring output (f_out). The output signal is selected by the LDS and FDS bits in the
serial programming data.
I Clock input for the 22-bit shift register. One bit of data is shifted into the shift register on a rising edge of the clock.
I
Serial data input. Data is transferred to the corresponding latch (RF1-ref counter, RF1-prog. counter, RF2-ref. counter, RF2-prog. counter)
according to the control bits settings in the serial programming data.
I
Load enable signal input. When the LE bit is set to “H”, data in the shift register is transferred to the corresponding latch ac cording to the
control bits settings in the serial programming data.
– Ground for the RF2-PLL section.
I Prescaler complimentary input for the RF2-PLL section. This pin should be grounded via a small capacitor.
I Prescaler input for the RF2-PLL. Connection to an external VCO should be via AC coupling.
– Ground for the RF2-PLL section.
O Charge pump output for the RF2-PLL section. Phase detector characteristics can be reversed using the FC-bit.
I Power supply for the RF2-PLL charge pump. (Independent of pin 2)
– Power supply voltage input pin for the RF2-PLL section. When power is OFF, latched data for RF2-PLL is lost.
4 Fujitsu Microelectronics, Inc.
Vcc₁
Vp₁
Do₁
GND₁
fin₁
Xfin₁
GND₁
OSC_IN
OSC_OUT
LD/f_OUT
1
20
2
19
3
18
4
17
5 _{TOP 16}
6 ^VIEW ₁₅
7
14
8
13
9
12
10
11
Vcc₂
Vp₂
Do₂
GND₂
fin₂
Xfin₂
GND₂
LE
Data
Clock
(FPT-20P-M03)