MB15U36 Datasheet, PDF (15/23 Pages) Fujitsu Component Limited. – Dual PLL Frequency Synthesizer with On-Chip Prescaler

Dual PLL Frequency Synthesizer with On-Chip Prescaler
Functional Descriptions
Table 4. Charge Pump Current Setting (CMC)
CMC
Current Value
L
1 x Do
H
4 x Do
Table 5. Charge Pump Output Impedance Setting (ZC)
ZC
Do Output Impedance
L
Normal output
H
High impedance
Table 6. LD/fout Output Select Data Setting
LDS_RF1
L
L
H
H
X
X
X
X
L
L
H
H
LDS_RF2
L
H
L
H
L
L
H
H
L
H
L
H
Note: X = Don’t care
FDS_RF1
L
L
L
L
L
H
L
H
H
H
H
H
FDS_RF2
L
L
L
L
H
L
H
L
H
H
H
H
LD/f_OUT Output Signal
Disabled
LD signal (RF2 lock detect)
LD signal (RF1 lock detect)
LD signal (RF1/RF2 lock detect)
f_OUT (Output fr_RF2)
f_OUT (Output fr_RF1)
f_OUT (Output fp_RF2)
f_OUT (Output fp_RF2)
Fastlock
RF2 counter reset
RF1 counter reset
RF1/RF2 counter reset
Table 7. Binary 11-bit Programmable Counter Data Setting
Divide
Ratio
(N)
3
4
.
2047
N
N
N
N
N
N
N
N
N
N
N
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
0
0
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
1
1
1
Note: Divide ratio less than 3 is prohibited.
16 Fujitsu Microelectronics, Inc.