MB15U36 Datasheet, PDF (16/23 Pages) Fujitsu Component Limited. – Dual PLL Frequency Synthesizer with On-Chip Prescaler

MB15U36
Functional Descriptions
Table 8. Binary 7-bit Swallow Counter Data Setting
Divide
Ratio
(A)
0
1
.
127
A
A
A
A
A
A
A
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
.
.
.
.
.
.
.
1
1
1
1
1
1
1
Note: Divide ratio (A) range = 0 to 127
Table 9. Prescaler Data Setting (SW)
Prescaler
Divide Ratio
SW = “L”
SW = “H”
RF1-PLL
64/65
128/129
RF2-PLL
64/65
128/129
Power-Saving Mode (Intermittent Mode Control)
• The intermittent mode control circuit greatly reduces the PLL power consumption by shuting down various internal functions, as
shown in Table 10, depending upon the settings of the power save (PS) bits. Setting the PS bits to “H” enters the corresponding PLL
into the power-saving mode. See the Electrical Characteristics chart for the specific value of current when in the power-saving mode.
• The phase detector output, Do, becomes high impedance.
• Serial data can be entered while in the power-saving mode.
• Setting the PS pins “L” releases the power-saving mode, returning the selected PLL to normal operation.
Note: When power (V_CC) is first applied, the device must be in standby mode, PS = High, for at least 1µs.
Table 10. Power Save Internal Shutdown Logic (PS)
PS_RF2
H
L
H
L
PS_RF1
H
H
L
L
RF2-PLL Counters
OFF
ON
OFF
ON
RF1-PLL Counters
OFF
OFF
ON
ON
OSC Input Buffer
OFF
ON
ON
ON
Fujitsu Microelectronics, Inc. 17