MB15U36 Datasheet, PDF (14/23 Pages) Fujitsu Component Limited. – Dual PLL Frequency Synthesizer with On-Chip Prescaler

MB15U36
Functional Descriptions
Programmable Counter
LSB
Data Flow
MSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
CC A A A A A A A N N N N N NN NNNN S P
N N 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 10 11 W S
12
CNT1, 2
Control bits
N1 to N11
Divide ratio setting bits for the programmable counter (3 to 2,047)
A1 to A7
Divide ratio setting bits for the swallow counter (0 to 127)
SW
Divide ratio setting bit for the prescalers
(64/65 or 128/129 for the RF1-PLL and RF2-PLL)
PS
Power saving mode control bit
Note: Input Data with MSB first.
[Table 1]
[Table 7]
[Table 8]
[Table 9]
[Table 10]
Table 2. Binary 15-bit Programmable Reference Counter Data Setting
Divide
Ratio
(R)
R
15
R
14
R
13
R
12
R
11
R
10
R
9
R
8
R
7
R
6
3
0
0
0
0
0
0
0
0
0
0
4
0
0
0
0
0
0
0
0
0
0
.
.
.
.
.
.
.
.
.
.
.
32767
1
1
1
1
1
1
1
1
1
1
Note: Divide ratio less than 3 is prohibited.
Table 3. Phase Comparator Phase Switching Data Setting
fr > fp
fr = fp
fr < fp
VCO polarity
Do_{RF1-PLL,RF2-PLL}
FC_{RF1-PLL,RF2-PLL} = “H” FC_{RF1-PLL,RF2-PLL} = “L”
H
L
Z
Z
L
H
(1)
(2)
VCO output
frequency
Notes: 1) Z = High-impedance
2) The FC bit should be set depending upon the VCO and LPF polarity
R
R
R
5
4
3
0
0
0
0
0
1
.
.
.
1
1
1
VCO input voltage
R
R
2
1
1
1
0
0
.
.
1
1
(1)
(2)
Fujitsu Microelectronics, Inc. 15