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MB15U36 Datasheet, PDF (20/23 Pages) Fujitsu Component Limited. – Dual PLL Frequency Synthesizer with On-Chip Prescaler
Application Example: Fastlock Mode
OUTPUT
LPF
VCO
TCXO
1000 pF
1000 pF
1000 pF
MB15U36
3V
3V
.1 µF
.1 µF
From Controller
LD/fOUT OSCOUT OSCIN GND1 Xfin1
fin1
GND1
Do1
Vp1
Vcc1
10
9
8
7
6
5
4
3
2
1
MB15U36
11
12
Clock Data
13
14
15
LE
GND2 Xfin2
16
17
18
19
20
fin2
GND2
Do2
Vp2
Vcc2
1000 pF
1000 pF
3V
3V
OUTPUT
VCO
LPF
.1 µF
.1 µF
Notes: 1) Package Type: 20-pin SSOP
2) Clock, Data, LE: Insert a pull-down or pull-up resistor as needed to prevent oscillation when the terminals are left open
3) The Fastlock mode is controlled by the LDS/FDS bits and the CMCRF1 bit. When the CMCRF1 bit is set to “H” (the RF1 charge pump current is increased
4x normal mode), the LD/fout pin (open drain output) is “L”, enabling the parallel resistor in the loop filter. This effectively increases the LPF bandwidth,
allowing the loop to lock faster. After the loop has locked onto a new frequency, the CMCRF1 bit is set to “L”, forcing the LD/fout output pin into a high
impedance state and returning the LPF bandwidth back to its original value.
Fujitsu Microelectronics, Inc. 21