MB15U36 Datasheet, PDF (17/23 Pages) Fujitsu Component Limited. – Dual PLL Frequency Synthesizer with On-Chip Prescaler

Dual PLL Frequency Synthesizer with On-Chip Prescaler
Serial Data Input Timing
1st data
Data
MSB
Control bit Invalid data
2nd data
LSB
Clock
t1
t2
t3
t7
LE
Table 11. Timing Parameters
Parameter
t1
t2
t3
t4
Min.
Typ.
Max.
Unit
20
–
20
–
30
–
–
ns
–
ns
–
ns
30
–
–
ns
Parameter
t5
t6
t7
Notes: 1) On the rising edge of the clock, one bit of the data is transferred into the shift register.
2) LE should be set to “L” when the data is transferred into the shift register.
t6
t4
t5
Min.
Typ.
Max.
Unit
100
–
–
ns
20
–
–
ns
100
–
–
ns
Power-ON Timing
OFF
VCC
Clock
Data
LE
PS
ON
tV ≥ 1 µS
(1)
(2)
(1) PS = H (power-saving mode) at Power-ON
(2) Input serial data 1µs later after power supply remains stable (V_CC > 2.2V).
(3) Release power-saving mode (PS: H Æ L) 100ns later after setting serial data.
18 Fujitsu Microelectronics, Inc.
tPS ≥ 100 nS
(3)