MB15F63UL Datasheet, PDF (17/36 Pages) Fujitsu Component Limited. – Dual Serial Input PLL Frequency Synthesizer

MB15F63UL
■ PHASE COMPARATOR OUTPUT WAVEFORM
frRF
fpRF
tWU
tWL
LD
(FC bit = “H”)
DoRF
(FC bit = “L”)
DoRF
• LD Output Logic
IF-PLL section
Locking state/Power saving state
Locking state/Power saving state
Unlocking state
Unlocking state
RF-PLL section
Locking state/Power saving state
Unlocking state
Locking state/Power saving state
Unlocking state
LD output
H
L
L
L
Notes : • Phase error detection range : −2π to +2π
• Pulses on Do signal during locked state are output to prevent dead zone.
RF-PLL section :
• LD output becomes “L” when phase is tWU or more. LD output becomes “H” when phase error is
tWL or less and continues to be so for ten cycles or more.
• tWU and tWL depend on fin input frequency.
tWU ≥ 1 / (fin / 16) [s] ex.) fin = 1629.9 MHz : tWU ≥ 9.82 ns
tWL ≤ 2 / (fin / 16) [s]
: tWL ≤ 19.63 ns
IF-PLL section
• LD output becomes “L” when phase is tWU or more. LD output becomes “H” when phase error
is tWL or less and continues to be so for three cycles or more.
• tWU and tWL depend on OSCin input frequency.
tWU ≥ 2 / fosc [s]
ex.) fosc = 13.0 MHz : tWU ≥ 153 ns
tWL ≤ 4 / fosc [s]
: tWL ≤ 256 ns
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