MB15F63UL Datasheet, PDF (15/36 Pages) Fujitsu Component Limited. – Dual Serial Input PLL Frequency Synthesizer

MB15F63UL
3. Power Saving Mode (Intermittent Operation)
PSIF
ExternalPIN
SerialData
IFPLL
PSRF
ExternalPIN
SerialData
0
0
Power save
0
0
0
1
Power save
0
1
1
0
Power save
1
0
1
1
Active
1
1
RFPLL
Power save
Power save
Power save
Active
The intermittent operation allows internal circuits to operate only when required and to stop otherwise. It is
designed to control the power consumed by the entire circuit block. However, if the circuit starts operating directly
from a stop state, the phase relation is undefined, even when the comparison frequency (fp) is the same as the
reference frequency (fr) input to the phase comparator. As a result, the phase comparator generates excessive
error signals, causing the problem of unlocking the PLL. To solve this problem, the intermittent operation control
has been implemented to control fluctuations in the locked frequency by performing forcible phase adjustment
at the beginning of operation.
• Operation mode
The set channel and crystal oscillator circuit are in operation and the PLL performs normal operation.
• Power save mode
This mode realizes low current consumption by stopping the circuits which will not cause any problem even when
stopped. In this condition, the standard consumption current is 0.1 µA per channel with the maximum of 10 µA.
At this point, Do and LD are set to the same levels as when the PLL was locked. The Do enters a high impedance
state, and the voltage input to the voltage control oscillator (VCO) remains the same as the voltage for operation
mode (i.e. locked state) with the time constant of the low pass filter. Therefore, the VCO output frequency can
be maintained almost at the same level as the lock frequency.
Notes : • When power (VCC) is first applied, the device must be in power saving mode (external pin = L, due to the
undefined serial data) .
• The serial data input after the power supply became stable, and then the power saving mode is released
after completed the data input.
OFF
VCC
ON
tv ≥ 1 µs
CLK
Data
LE
PS
tps ≥ 100 ns
(1)
(2)
(3)
(1) PS = L (power saving mode) at Power ON
(2) Set serial data 1 µs later after power supply remains stable (VCC ≥ 2.2 V) .
(3) Release power saving mode (PS : L → H)
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