MB15F63UL Datasheet, PDF(10/36 Page) Fujitsu Component Limited. – Dual Serial Input PLL Frequency Synthesizer

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MB15F63UL Datasheet, PDF (10/36 Pages) Fujitsu Component Limited. – Dual Serial Input PLL Frequency Synthesizer

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MB15F63UL

â FUNCTIONAL DESCRIPTION

1. Serial Data Input

Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference

divider and the programmable divider separately.

Binary serial data is entered through the Data pin.

One bit of data is shifted into the shift register on the rising edge of the Clock. When the LE signal pin is taken

high, stored data is latched according to the control bit data.

The following table shows the shift register configuration and combinations of data transfer control bits.

LSB

Destination of serial data

MSB

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

R9 R10 R11 R12 R13 R14 CS SW FC

IF IF IF IF IF IF IF IF IF

A1 A2 A3 A4 A5 A6 A7 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 PS

IF IF IF IF IF IF IF IF IF IF IF IF IF IF IF IF IF IF IF

F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 A1 A2 A3 A4 N1 N2 N3

RF RF RF RF RF RF RF RF RF RF RF RF RF RF RF RF RF RF RF RF RF RF RF RF RF RF RF

N4 N5 N6 N7 R1 R2 R3 R4 R5 R6 FC TM TM TM TM TM TM TM TM

RF RF RF RF RF RF RF RF RF RF RF C 1 2 3 4 5 6 7

Note : Start data input with MSB first.

2. Setting data

a) Fractional-N Synthesizer in the RF-PLL section

Set each setting value for the Fractional-N Synthesizer counter, according to the following equations.

fvcoRF = NTOTAL Ã fOSC Ã· R

NTOTAL = P Ã N + A + 3 + F/Q

F: Set the numerator of fractional division with its fractional portion discarded.

When value F is even-numbered as a result of the division calculation, â1â is added to F.

b) Integer-N Synthesizer in the IF-PLL section

The Integer-N Synthesizer counter is set, according to the following equations.

fvcoIF = NTOTAL Ã fOSC Ã· R

NTOTAL = P Ã N + A

fvcoRF/fvcoIF

NTOTAL

fosc

: Output frequency of externally connected VCO

: Total number of divisions from prescaler input to phase comparator input

: Reference oscillation frequency (OSCin input frequency)

: RF side : Setting value for binary 6-bit reference counter (1 to 63)

IF side : Setting value for binary 14-bit reference counter (1 to 16383)

: RF side : Division ratio for prescaler (16)

IF side : Division ratio for prescaler (8, 16)

: RF side : Setting value for binary 7-bit programmable counter (5 to 127)

IF side : Setting value for binary 11-bit programmable counter (3 to 2047)

: RF side : Setting value for binary 4-bit swallow counter (0 to 15)

IF side : Setting value for binary 4-bit swallow counter (0 to 127, A < N)

: Numerator of fractional division (0 to 1048575, F < Q)

: Denominator of fractional division (220 = 1048576)

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