MB15F63UL Datasheet, PDF (14/36 Pages) Fujitsu Component Limited. – Dual Serial Input PLL Frequency Synthesizer

MB15F63UL
Table 10 - LD/fout output setting
LD/fout
LDS T1 T2
LD output
0
frIF
1
frRF 1
fout
fpIF 1
fpRF 1
⎯⎯
0
0
1
0
0
1
1
1
Maximum operating
frequency [MHz]*
1800
2000
* : The maximum operating frequency varies depending on the output state of the LD/fout pin (LD output or fout
output).
Table 11 - Comparator polarity setting
FC = “1” FC = “0”
Do
Do
fp < fr
H
L
fr < fp
L
H
fr = fp
Z
Z
VCO Polarity
(1)
(2)
Note : Set the FC bit in accordance with the low pass filter and VCO polarity, when designing a PLL frequency
synthesizer.
high
When VCO is (1)
FC : “H”
When VCO is (2)
FC : “L”
VCO
output
Frequency
(1)
(2)
high
VCO Input Voltage
14