MB15F63UL Datasheet, PDF (16/36 Pages) Fujitsu Component Limited. – Dual Serial Input PLL Frequency Synthesizer

MB15F63UL
4. Serial Data Input Timing
Divide ratio is performed through a serial interface using the Data pin, Clock pin, and LE pin.
Setting data is read into the shift register at the rise of the Clock signal, and transferred to a latch at the rise of
the LE signal. The following diagram shows the data input timing.
1st. data
Control bit
2nd. data
Invalid data
Data
CLK
MSB
∼
LSB
∼
∼
t1
t2
t5
t4
LE
t0
∼
t3
t6
100 ns ≤ t0, t6 20 ns ≤ t1, t2, t4 30 ns ≤ t3, t5
LE should be “L” when the data is transferred into the shift register.
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