MC68HC05SR3D Datasheet, PDF (90/96 Pages) Freescale Semiconductor, Inc – Microcontrollers

CLR
LDX
BSET
LDA
STA
BSET
JSR
CLR
PCR
#$00
1,PCR
#$00
$1900,X
0,PCR
DELAY
PCR
;reset PCR
;load index register with 00
;set ELAT bit
;load data=00 in to A
;latch data and address
;program
;call delay subroutine for 1ms
;reset PCR
A.5
Mask Option Register (MOR)
The Mask Option Register (MOR) contains programmable EPROM bits to control mask options,
and cannot be changed in User mode. The erased state are zeros. This register is latched upon
reset going away.
Mask Option Register (MOR)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0FFF
SMD SEC TMR2 TMR1 TMR0 RC unaffected
SMD — SLOW Mode at Power-on
When programmed to “1”, this bit enables SLOW mode at power-up. Operating frequency,
f_OP =f_OSC ÷ 2 ÷ 16 = f_OSC ÷ 32.
SEC — EPROM Security
When programmed to “1”, this bit disables some functions of the Bootstrap mode, preventing
external reading of EPROM content.
TMR2:TMR0 — Power-on Reset Delay
The amount Power-On Reset delay is set by programming these three bits. The delay is selected
as follows:
A
TMR2
0
0
0
0
1
1
1
1
TMR1
0
0
1
1
0
0
1
1
TMR0
0
1
0
1
0
1
0
1
Delay (Instruction Cycles)
256
512
1024
2048
4096
8192
16384
32768
Freescale
A-4
MC68HC705SR3
TPG
MC68HC05SR3