MC68HC05SR3D Datasheet, PDF (60/96 Pages) Freescale Semiconductor, Inc – Microcontrollers

Table 8-3 Branch instructions
Relative addressing mode
Function
Mnemonic Opcode # Bytes # Cycles
Branch always
BRA
20
2
3
Branch never
BRN
21
2
3
Branch if higher
BHI
22
2
3
Branch if lower or same
BLS
23
2
3
Branch if carry clear
BCC
24
2
3
(Branch if higher or same)
(BHS)
24
2
3
Branch if carry set
BCS
25
2
3
(Branch if lower)
(BLO)
25
2
3
Branch if not equal
BNE
26
2
3
Branch if equal
BEQ
27
2
3
Branch if half carry clear
BHCC
28
2
3
Branch if half carry set
BHCS
29
2
3
Branch if plus
BPL
2A
2
3
Branch if minus
BMI
2B
2
3
Branch if interrupt mask bit is clear
BMC
2C
2
3
Branch if interrupt mask bit is set
BMS
2D
2
3
Branch if interrupt line is low
BIL
2E
2
3
8
Branch if interrupt line is high
Branch to subroutine
BIH
2F
2
3
BSR
AD
2
6
Function
Branch if bit n is set
Branch if bit n is clear
Set bit n
Clear bit n
Table 8-4 Bit manipulation instructions
Mnemonic
BRSET n (n=0–7)
BRCLR n (n=0–7)
BSET n (n=0–7)
BCLR n (n=0–7)
Addressing modes
Bit set/clear
Bit test and branch
Opcode # Bytes # Cycles Opcode # Bytes # Cycles
2•n
3
5
01+2•n 3
5
10+2•n 2
5
11+2•n 2
5
Freescale
8-6
CPU CORE AND INSTRUCTION SET
TPG
MC68HC05SR3