MC68HC05SR3D Datasheet, PDF (28/96 Pages) Freescale Semiconductor, Inc – Microcontrollers

3
INTERNAL
MC68HC05
CONNECTIONS
DATA DIRECTION
REGISTER BIT
LATCHED OUTPUT
DATA BIT
OUTPUT
REGINISPTUETR
BIT
INPUT I/O
I/O PIN
Figure 3-1 Port I/O Circuitry
3.1.2 Port Data Direction Registers
Each port pin may be programmed as an input by clearing the corresponding bit in the DDR, or
programmed as an output by setting the corresponding bit in the DDR. The DDR for Port A, B, C,
and D are located at $04, $05, $06 and, $07 respectively. The DDRs are cleared by reset.
Note:
A “glitch” may occur on an I/O pin when selecting from an input to an output unless the
data register is first preconditioned to the desired state before changing the
corresponding DDR bit from a “0” to a “1”.
3.2
Port A — Keyboard Interrupts (KBI)
Port A is configured for use as keyboard interrupts when the KBIE bit is set in the Miscellaneous
Control Register (MCR). Individual keyboard interrupt port pins are also maskable by setting
corresponding bits in the Keyboard Interrupt Mask Register.
See Section 5.2.2.4 for details on the keyboard interrupts.
3.3
PD0:PD5 — ADC Inputs
When the ADON bit is set in the ADC Status and Control Register, PD0 to PD3 are configured as
ADC inputs AN0 to AN3 respectively. PD4 and PD5 are configured as V_RL and V_RH respectively.
See Section 7 for details on the Analog to Digital Converter.
Freescale
3-2
INPUT/OUTPUT PORTS
TPG
MC68HC05SR3