MC68HC05SR3D Datasheet, PDF (54/96 Pages) Freescale Semiconductor, Inc – Microcontrollers

Table 7-1 ADC Channel Assignments
CH2 CH1 CH0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Channel
0
1
2
3
4
5
6
7
Selected Signal
AD0 on PD0
AD1 on PD1
AD2 on PD2
AD3 on PD3
V_RH
V_RL
(V_RH–V_RL) ÷ 4
(V_RH–V_RL) ÷ 2
Using a port D pin as both an analog and digital input simultaneously is prohibited. When the ADC
is enabled (ADON=1) and one of channels 0 to 5 is selected, the corresponding Port D pin will
appear as a logic zero when read from the Port Data Register.
7 ^7.3
ADC Data Register (ADDR)
The ADDR stores the result of a valid ADC conversion when the COCO bits is set in ADSCR.
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0F AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 uuuu uuuu
7.4
ADC during Low Power Modes
The ADC continues normal operation in WAIT mode. To reduce power consumption in WAIT
mode, the ADON and ADRC bits in the ADSCR should be cleared if the ADC is not used. If the
ADC is in use and the internal bus clock is above 1MHz, it is recommended that the ADRC bit be
cleared.
In STOP mode, the ADC stops operation.
Freescale
7-4
ANALOG TO DIGITAL CONVERTER
TPG
MC68HC05SR3