MC68HC05SR3D Datasheet, PDF (55/96 Pages) Freescale Semiconductor, Inc – Microcontrollers

8
CPU CORE AND INSTRUCTION SET
This section provides a description of the CPU core registers, the instruction set and the
addressing modes of the MC68HC05SR3.
8.1
Registers
The MCU contains five registers, as shown in the programming model of Figure 8-1. The interrupt
stacking order is shown in Figure 8-2.
7
0
Accumulator
7
0
8
Index register
15
7
0
Program counter
15
7
0
0000000011
Stack pointer
7
0
1 1 1 H I N Z C Condition code register
Carry / borrow
Zero
Negative
Interrupt mask
Half carry
Figure 8-1 Programming model
8.1.1 Accumulator (A)
The accumulator is a general purpose 8-bit register used to hold operands and results of
arithmetic calculations or data manipulations.
MC68HC05SR3
CPU CORE AND INSTRUCTION SET
TPG
Freescale
8-1