MC908AP8CFBE Datasheet, PDF (84/324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Clock Generator Module (CGM)
1. Choose the desired bus frequency, f_BUSDES, or the desired VCO frequency, f_VCLKDES; and then
solve for the other.
The relationship between f_BUS and f_VCLK is governed by the equation:
× f_VCLK = 2^P × f_CGMPCLK = 2^P × 4 f_BUS
where P is the power of two multiplier, and can be 0, 1, 2, or 3
2. Choose a practical PLL reference frequency, f_RCLK, and the reference clock divider, R. Typically,
the reference is 32.768kHz and R = 1.
Frequency errors to the PLL are corrected at a rate of f_RCLK/R. For stability and lock time reduction,
this rate must be as fast as possible. The VCO frequency must be an integer multiple of this rate.
The relationship between the VCO frequency, f_VCLK, and the reference frequency, f_RCLK, is
f_VCLK = ^2----P_R----N---(f_RCLK)
where N is the integer range multiplier, between 1 and 4095.
In cases where desired bus frequency has some tolerance, choose f_RCLK to a value determined
either by other module requirements (such as modules which are clocked by CGMXCLK), cost
requirements, or ideally, as high as the specified range allows. See Chapter 22 Electrical
Specifications.
Choose the reference divider, R = 1.
When the tolerance on the bus frequency is tight, choose f_RCLK to an integer divisor of f_BUSDES,
and R = 1. If f_RCLK cannot meet this requirement, use the following equation to solve for R with
practical choices of f_RCLK, and choose the f_RCLK that gives the lowest R.
R
=
round
R_M
A
X
×
⎧⎛
⎨⎜
⎩⎝
f--_{V----fC--R--L--C-K--L-D--K--E----S- ⎠⎟⎞}
–
i
nte
ge
⎛
r⎜
⎝
f--_{V----fC--R--L--C-K--L-D--K--E----S- ⎠⎟⎞}
⎫
⎬
⎭
3. Calculate N:
N
=
rou
nd
⎛
⎜
⎝
R-----f-×_{-R---C-f--V-L---CK---L--×-K----2D---P-E---S--⎠⎟⎞}
4. Calculate and verify the adequacy of the VCO and bus frequencies f_VCLK and f_BUS.
f_VCLK = ^2----P_R----N---(f_RCLK)
f_BUS = ₂-^f-^V-_P--^C-_×-^L---^K₄-
MC68HC908AP Family Data Sheet, Rev. 4
84
Freescale Semiconductor