MC908AP8CFBE Datasheet, PDF (291/324 Pages) Freescale Semiconductor, Inc – Microcontrollers

LVI Status Register
20.3.4 Forced Reset Operation
In applications that require V_DD to remain above the V_TRIPF1 level, enabling LVI resets allows the LVI
module to reset the MCU when V_DD falls below the V_TRIPF1 level. In the CONFIG1 register, the LVIPWRD
and LVIRSTD bits must be at logic 0 to enable the LVI module and to enable LVI resets.
20.3.5 Voltage Hysteresis Protection
Once the LVI has triggered (by having V_DD fall below V_TRIPF1), the LVI will maintain a reset condition until
V_DD rises above the rising trip point voltage, V_TRIPR1. This prevents a condition in which the MCU is
continually entering and exiting reset if V_DD is approximately equal to V_TRIPF1. V_TRIPR1 is greater than
V_TRIPF1 by the hysteresis voltage, V_HYS.
20.4 LVI Status Register
The LVI status register (LVISR) indicates if the V_DD voltage was detected below V_TRIPF1 or V_REG voltage
was detected below V_TRIPF2.
Address:
Read:
Write:
Reset:
$FE0F
Bit 7
LVIOUT
0
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 20-3. LVI Status Register
1
Bit 0
0
0
0
0
LVIOUT — LVI Output Bit
This read-only flag becomes set when the V_DD or V_REG falls below their respective trip voltages. Reset
clears the LVIOUT bit.
Table 20-1. LVIOUT Bit Indication
V_DD, V_REG
V_DD > V_TRIPR1
and
V_REG > V_TRIPR2
V_DD < V_TRIPF1
or
V_DD < V_TRIPF2
V_TRIPF1 < V_DD < V_TRIPR1
or
V_TRIPF2 < V_REG< V_TRIPR2
LVIOUT
0
1
Previous value
20.5 LVI Interrupts
The LVI module does not generate interrupt requests.
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
289